2026-2027 Funded Projects
Funded Projects for AY 2026-2027
Thanks to our industry and university members, we are currently able to fund the below proposed projects for this academic year (August 2026- July 2027). Projects began at the start of the Fall semester, on August 16th. Congratulations to our PIs for their successful proposals.
Theme 1: "Gate Scaling of 2D Transistors with a Carbon-Dot van der Waals Interfacial Layer"
PI - Qing Cao
“2D nanomaterials are promising channel materials for constructing next-generation nanoelectronics. Their dangling-bond-free, atomically smooth surfaces enable fast carrier transport even at an intrinsic sub-1-nm channel thickness. In transistors, these 2D channels must be insulated from the gate electrode by a dielectric layer, whose properties determine device performance, power consumption, and reliability. To meet targets set in the IRDS, this gate dielectric must achieve an equivalent oxide thickness (EOT) below 1 nm, leakage current density below 10-2 A·cm-2, and dielectric strength greater than 10 MV·cm-1. This dielectric layer must also develop a stable, clean interface with 2D channels to preserve
fast carrier transport for maximizing output current density, ensure high gate efficiency for low-voltage operation with sharp subthreshold swing (SS), allow threshold voltage (VT) controllability, provide operational stability under bias stress, and enable top-gated device structure for circuit integration.”
Theme 1: "Precise Synthesis of 2D Materials for Advanced Electronic and Optoelectronic Devices"
PI - Wenjuan Zhu
“We propose a composable chiplet-based SoC architecture, constructed around a double-sided Si interposer. We plan to design a new series of logic+memory ML accelerator chiplets, which (1) incorporate emerging and heterogeneous memory technologies, (2) contain decomposed logic capabilities based on the needs of different ML models, (3) are laid out to maximize thermal dissipation in the SoC, and (4) potentially incorporate in-memory computing (IMC) capabilities. Along with these chiplets, our composable SoC also incorporates CPU cores, potentially GPU cores, and voltage regulators, with design space exploration (DSE) to ensure that the resulting SoC floorplan meets stringent thermal targets.”
Theme 1: "Spin torques and Giant Magnetoresistance from Altermagnetism"
PI - Axel Hoffmann
“Non-collinear antiferromagnets, while exhibiting zero net magnetization, manifest a pronounced spin splitting due to the interplay between their crystal symmetry and magnetic order, known as altermagnetism. Our goal is to leverage altermagnetism in non-collinear antiferromagnets to realize unconventional spin torques and giant magnetoresistance (GMR), a breakthrough that could serve as a building-block for antiferromagnetic information devices, enabling efficient logic and memory technologies.”
Theme 1 & 2: "Butt-coupled Lasers on Silicon Photonic Platforms via Remote Epitaxy and Wafer-Scale Self-Assembly"
PIs - Hyunseok Kim, Minjoo Lawrence (Larry) Lee
“We aim to develop wafer-scale heterogeneous integration of III-V lasers onto silicon photonic wafers, leveraging remote epitaxy and scalable transfer processes. This approach addresses the challenges of existing III-V/Si integration techniques, such as wafer-to-wafer bonding, die-to-wafer bonding, photonic wire bonding, and monolithic approaches, and can dramatically improve yield, scalability, reliability, and performance.”
Theme 1 & 2: "Heterogeneous Integration of Lithium Niobate on III-V/Si Substrates"
PIs - Minjoo Lawrence (Larry) Lee, Chris Anderson
“Our overarching goal is to create platforms that reimagine photonic device structures to facilitate heterogeneous integration. Thin-film lithium niobate (TFLN), which consists of a bonded layer of lithium niobate on an oxidized silicon substrate, is emerging as a powerful platform for data communication owing to its combination of low propagation loss, strong electro-optic coefficient, and efficient frequency comb generation. Heterogeneous integration of III-V gain with TFLN modulators and frequency combs would enable compact, low-cost optical transceivers for near-term commercial applications in data centers.”
Theme 2: "High Throughput Thermal Metrology from Devices to Dies"
PI - David Cahill
“The goal is to improve metrology for thermal conductivity and thermal boundary resistance across length scales from nanoscale materials to heterogenous integration.”
Theme 2: "Strain-Induced Mobility Enhancement in 2D Material Transistor"
PIs - Arend van der Zande, Shaloo Rakheja
“The goal of this project is to apply process induced strain techniques to enhance transport in 2D field effect transistors. We propose to model how process induced strains from thin film deposition transfer into 2D material monolayers, and leverage process induced strain techniques to enhance mobility in 2D transistors.”
Theme 3: "Exploring Novel Memory Architecture Using Emerging Devices"
PIs - Saugata Ghose, Shaloo Rakheja
“As the ASAP Center produces new memory devices under Themes 1 and 2, we will explore how to integrate these devices into practical memory architectures that can be fabricated and used at scale. We will develop detailed models of devices being developed by other ASAP projects, and incorporate them into an extended version of our open-source memory architecture simulator, to allow for early-stage (i.e., pre-device-fab) exploration of ideal memory array topologies, architectural properties, and potential for processing-in-memory.”
Theme 3: "Designing a Chipset-Based Composable Machine Learning Architecture"
PIs - Saugata Ghose, Josep Torrellas
“TWe propose a composable chiplet-based SoC architecture, constructed around a double-sided Si interposer. We plan to design a new series of logic+memory ML accelerator chiplets, which (1) incorporate emerging and heterogeneous memory technologies, (2) contain decomposed logic capabilities based on the needs of different ML models, (3) are laid out to maximize thermal dissipation in the
SoC, and (4) potentially incorporate in-memory computing (IMC) capabilities. Along with these chiplets, our composable SoC also incorporates CPU cores, potentially GPU cores, and voltage regulators, with design space exploration (DSE) to ensure that the resulting SoC floorplan meets stringent thermal targets.”