2023-2024 Funded Projects

Funded Projects for AY 2023-2024

Thanks to our industry and university members, we are currently able to fund four proposed projects for this academic year (August 2023- July 2024). Projects began at the start of the Fall semester, on August 16th, 2023. Congratulations to our PIs for their successful proposals. The ASAP leadership team is expecting to support additional projects as we gather additional support from new members this year.

Student working with syringe and test tube in lab

Project 1: Topological Semimetals by Superconformal CVD

Theme 1 - Electrical and Optical Interconnects

PIs - John Abelson, Gregory Girolami 
Supported Students - Joe Lastowski, Dr. Laurent Souqui

"In this project, we will address a key challenge in semiconductor technology: to develop the first methods to deposit topological semimetals conformally by CVD or ALD in deep features. The overarching goal is to develop a superconformal chemical vapor deposition route to completely fill interconnect structures with low-resistivity topological semimetals."

Student working with syringe and test tube in lab

Project 2: Photonic Interface for Smart Packaging

Theme 2 - Heterogeneous Integration

PIs - Lynford Goddard, Kent Choquette, Paul Braun
Supported Students - Nikita Duggar, Nisha Kolagotla

“The overarching project goal is to demonstrate a robust interface of 3-dimensional optical interconnects between 2-dimensional optical source and detector array chips for intra-chip and inter-chip data transfer. We propose to overcome the packaging interface challenge of routing input/output optical signals onto an optoelectronic chip.”

Insert caption here

Project 3: Exploring Novel Memory Architecture Using Emerging Devices

Theme 3 - Circuits and Architectures

PIs - Saugata Ghose, Shaloo Rakheja
Supported Students - Arjun Tyagi, Ankit Shukla, Minh S. Q. Truong, Dawei Xiong, Rahul Prabhu, Yiqui Sun

“As the ASAP Center produces new memory devices under Themes 1 and 2, we will explore how to integrate these devices into practical memory architectures that can be fabricated and used at scale. We will develop detailed models of devices being developed by other ASAP projects, and incorporate them into an extended version of our open-source memory architecture simulator, to allow for early-stage (i.e., pre-device-fab) exploration of ideal memory array topologies, architectural properties, and potential for processing-in-memory.”

Project 4: Strain-Induced Mobility Enhancement in 2D Material Transistor

Theme 2 - Heterogeneous Integration

PI - Arend van der Zande
Supported Students - Kevin Zhao, Yue Zhang, Mohammad Abir Hossain, Kelly Jiyoung Hwang, Joe Maduzia

“The goal of this project is to apply process induced strain techniques to enhance transport in 2D field effect transistors. We propose to model how process induced strains from thin film deposition transfer into 2D material monolayers, and leverage process induced strain techniques to enhance mobility in 2D transistors.” 

Project 5: Transfer-Printed Single-Crystalline Si Nanomembrane for High- Performance Junctionless MOSFET on BEOL

Theme 2 - Heterogeneous Integration

PI - Qing Cao
Supported Student - Sunny Wong

“The overarching goal of this project is to realize high-performance, BEOL-compatible CMOS circuits based on transferred-printed ultrathin single-crystalline Si membranes and fully-depleted junctionless transistors. We will develop a process to cultivate high-quality single-crystalline silicon nanomembranes from SOI wafers, and then roll-to-roll transfer them on wafer scale to completed CMOS substrates. Juntionless transistors with optimized structure will be fabricated on these stacked silicon nanomembranes under a restricted thermal budget.  They do not require any high-temperature doping step to form p-n junction during fabrication but can offer performance and scalability comparable to FEOL silicon MOSFETs.” 

Project 6: Transforming Future Computing Using Ferroelectric Devices

Theme 3 - Circuits and Architectures

PIs - Wenjuan Zhu, Shaloo Rakheja
Supported Students - Junzhe Kang, Hanwool Lee, Zijing Zhao, Ashwin Tunga

“The goal of this project is to create ferroelectric reconfigurable logic transistors and develop novel in-memory computing circuits, which will offer unique functionalities and significantly enhance both circuit density and energy efficiency. These ferroelectric circuits will have high potential in data-intensive applications from image processing to machine learning and artificial intelligence.”