Fall 2024 Industry Workshop & Advisory Board Meeting

Fall 2024 Industry Workshop & Advisory Board (IAB) Meeting

You are invited to attend the ASAP Center's in-person industry advisory board (IAB) meeting on November 7-8, 2024. Join us to learn more about the Center's latest research in CMOS+X semiconductors and microelectronics research. This is a great opportunity to meet UIUC faculty, students, and top semiconductor industry, national lab, and DoD members. The meeting will also include funded project research updates, a student poster session, and a keynote speaker presentation during dinner.

Register for free with the 'Register' button below, and find the Agenda, Keynote Details, and Travel/Accommodation information as those are finalized.

REGISTER FOR THE FALL 2024 IAB MEETING

Registration is free.

November 7-8, 2024

REGISTER NOW

 

Agenda - 

*All times in CT
Meeting Location: HMNTL 1000

Day 1 November 7, 2024
8:30 - 9:00 AM Registration & Breakfast
9:00 - 9:05 AM Welcome Remarks
Shaloo Rakheja, ASAP Center Director
9:05 - 9:25 AM Illinois Leadership in Semiconductor and Microelectronics
Minjoo (Larry) Lawrence Lee, Director of the Holonyak Micro & Nanotechnology Laboratory
9:25 - 9:40 AM Illinois Participation in Semiconductor Initiatives
Laurel Passantino, Assistant Dean for Research
9:40 - 10:35 AM ASAP Year in Review
Shaloo Rakheja, ASAP Center Director
Qing Cao, ASAP Associate Director
10:35 - 10:50 AM BREAK
10:50 - 12:20 PM Project Presentations
UIUC Faculty

10:50 - 11:20 AM 
Topological Semimetals by Superconformal CVD, Abelson and Girolami

11:20 - 11:50 AM 
Exploring Novel Memory Architecture Using Emerging Devices, Ghose and Rakheja

11:50 - 12:20 PM 
Photonic Interface for Smart Packaging, Goddard, Choquette, and Braun
12:20 - 1:20 PM LUNCH - HMNTL Atrium
1:20 - 2:50 PM

Project Presentations Continued
UIUC Faculty

1:20 - 1:50 PM
Strain-Induced Mobility Enhancement in 2D Material Transistor, van der Zande

1:50 - 2:20 PM 
Transfer-Printed Single-Crystalline Si Nanomembrane for High-Performance Junctionless MOSFET on BEOL, Cao

2:20 - 2:50 PM
Heterogeneous Integration of Lithium Niobate on III-V/Si Substrates, Lee and Anderson

2:50 - 3:00 PM BREAK
3:00 - 3:30 PM General Project Discussions with Industry Advisory Board (IAB)
Open to All
3:30 - 4:00 PM Special Faculty Presentation
Dr. Jose E Schutt-Aine, Electrical & Computer Engineering Professor
4:00 - 4:20 PM Institute for Inclusion, Diversity, Equity, & Access (IDEA) Talk
Ellen Wang Althaus, Assistant Dean for Strategic Diversity, Equity, and Inclusion Initiatives at the Grainger College of Engineering
4:20 - 4:30 PM Review of Evening and Day 2 Activities
Shaloo Rakheja, ASAP Center Director
4:30 - 6:00 PM
HMNTL 3rd Floor Atrium
Technical Forum and Networking 
Student Poster Session
6:00 PM
HMNTL 1st Floor Atrium
Dinner and Keynote Presentation 
Dr. Juan C. Rey, Vice-President of Government Programs at Siemens EDA
Day 2 November 8, 2024
8:00 - 8:30 AM Arrival & Breakfast
8:30 - 8:35 AM Day 2 Kickoff
Shaloo Rakheja, ASAP Center Director
8:35 - 9:00 AM Education and Workforce Development
Shaloo Rakheja, ASAP Center Director
9:00 - 9:10 AM START Supplement Progress Report
Nikita Duggar, Graduate Student in PI Lynford Goddard's Group
9:10 - 9:30 AM Semiconductor Ecosystem Overview
Jennifer Truman Bernhard, Head, Department of Electrical and Computer Engineering, Donald Biggar Willett Professor of Engineering
9:30 - 10:00 AM

Project Feedback Discussion
ASAP PIs and IAB

10:00 - 10:10 AM BREAK
10:10 - 11:10 AM Closed IAB Meeting
(NSF and IAB Only - HMNTL 1000)
Parallel Faculty Meeting - Strategic Planning for Year 3 & Beyond
(Center Director, Associate Director, and ASAP Researchers - HMNTL Atrium)
11:10 - 11:40 AM IAB Discussion and Wrap-Up
Open to All
11:40 - 11:45 PM Summary and Closing Remarks
Shaloo Rakheja, ASAP Center Director
11:45 - 12:00 PM Group Photographs
12:00 PM Adjourn, Lunch, & Depart

 

KEYNOTE DETAILS

Dr. Juan C. Rey

Vice-President of Government Programs at Siemens EDA

Title: Major Changes in the Semiconductor Industry – and the Impact on Electronics Design Automation

We are going through the largest technology/business change in the semiconductor industry since the combined transition from Bipolar to CMOS technology and from integrated Design/Manufacturing companies to a Fabless/Fabs industry.

The major developments triggered by 2.5/3D integration technological changes are pushing for new technical solutions for “advanced integration”, often blurring the lines between the design of integrated circuits, packages and boards. These changes are also impacting the traditional business models from basic IP blocks, through the design of the entire system, and even the manufacturing stage. 

Although it is not possible to predict how the next few years will develop until the industry aligns behind a new “roadmap”, it is possible to forecast the increased significance of two technologies that are already contributing to provide solutions to the design and manufacturing challenges: Digital Twins and Artificial Intelligence.

This talk will describe some examples of the latest EDA developments in this space and indicate the major directions where these technologies will continue delivering solutions in the years to come.

Juan C. Rey, vice-president of government programs at Siemens EDA, previously vice president of Engineering, Calibre, joined Mentor in 2001 as senior engineering director for Mentor’s industry-leading Calibre product line, directing all engineering activities for Calibre products.

Previously he was vice-president of Engineering at Exend Corporation, managing all software development and quality activities. Prior to that he was engineering director for Physical Verification at Cadence Design Systems.

Earlier positions include: manager/developer for Process Modeling and Parasitic Extraction at Technology Modeling Associates; visiting scholar/science and engineering associate at Stanford University; senior research engineer at INVAP, Argentina; and associate professor at Universidad Nacional del Comahue, Argentina.

Juan holds a degree in Nuclear Engineering from Instituto Balseiro, Universidad Nacional de Cuyo, Argentina. The author or co-author of numerous papers and conference presentations, he serves on the Executive Technology Advisory Board of Semiconductor Research Corporation (SRC) and at the SI2 Board of Directors and previously at the Industry Advisory Board of the UCLA Center for Domain-Specific Computing.

SPECIAL FACULTY PRESENTATION DETAILS

Dr. José Schutt-Ainé 

University of Illinois, Electrical and Computer Engineering

Title: Co-Design for Heterogeneous Integration

This talk focuses on current state-of-the-art, challenges and potential solutions for co-design. Electrical, thermal, and mechanical interactions across the chip-package-board domains can no longer be ignored. New modeling and simulation tools must accurately predict the physical (e.g. electro-thermal, thermo-mechanical, etc) coupling between multiple semiconductor components and the package/system that contains them. Current packaging roadmaps explore how design and analysis practices need to be defined in the context of heterogeneous integration. They address the traditional chip-package-board design flow as well as current capabilities and future challenges. The vision is to create an environment where design closure is achieved with a minimum number of iterations meeting all requirements for performance and cost. This environment must leverage from currently available technologies, namely intelligent materials, computing power, algorithms and artificial intelligence.

José E. Schutt-Ainé received the B.S. degree in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1981, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign (UIUC), Urbana, in 1984 and 1988, respectively. In 1989, he joined the Electrical and Computer Engineering Department as a member of the Electromagnetics and Coordinated Science Laboratories, where he is currently involved in research on signal integrity for high-speed digital and high-frequency applications. He is a consultant for several corporations. His current research interests include the study of signal integrity and the generation of computer-aided design tools for high-speed digital systems. He is an IEEE Fellow and served as Co-Editor-in-Chief of the IEEE Transactions on Components, Packaging and Manufacturing Technology (T-CPMT) from 2007 to 2018. He is an EPS Distinguished Lecturer and the recipient of the 2024 IEEE-EPS Outstanding Sustained Technical Contribution Award.

 

Accommodations and Travel

Airplane

Train

AMTRAK has service between Union Station in Chicago (CHI) and Illinois Terminal in Champaign (CHM).

Bus/Shuttle

  • Peoria Charter (private bus company) serves many different locations including both Chicago airports (O'Hare and Midway), Union Station in Chicago, and a number of Chicago suburbs. Pick up is available from Terminal 2 and Terminal 5 at the O'Hare International Airport with multiple drop-off points on-campus.
  • Greyhound (private bus company) has daily service between Chicago and Champaign. Pick up is available from downtown Chicago with drop-off at the Illinois Terminal in downtown Champaign.

A block of rooms has been reserved at TownePlace Suites Champaign Urbana/Campustown for guests to reserve a room at the discounted group rate. Please use this link to book by 12 PM CT on 11/04/2024. 

Other nearby hotel options include:
- Illini Union Hotel
- Hampton Inn Champaign Urbana

Parking is available at each of the recommended hotels. For those who do not wish to walk from their hotel to the event venue, a few parking meter spaces are available in the B-4 Parking Deck at the corner of University Ave/Mathews Ave. in Urbana (see image below). These are available on a first come, first serve basis.  Additional parking information is available here. 

B-4 North Campus Parking Deck, 1201 W. University Ave - Enter from Mathews Street
 

The Spring IAB Meeting will be held on the University of Illinois Urbana-Champaign Campus. The meeting will be held in the Nick Holonyak Micro and Nanotechnology Laboratory, Room 1000, located at 208 N Wright St, Urbana, IL 61801.

 

Contact

Please contact Shaloo Rakheja (rakheja@illinois.edu), Qing Cao (qingcao2@illinois.edu), or Mallory Gorman (magorma2@illinois.edu) for questions or concerns related to the event, or about becoming a memeber.